PIC18F4539T-E/ML【PDF 207/322 页】IC PIC MCU FLASH 12KX16 44QFN

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2002 Microchip Technology Inc.

Preliminary

DS30485A-page 283

PIC18FXX39

TABLE 23-18: MASTER SSP I2C BUS DATA REQUIREMENTS

Param.

No.

Symbol

Characteristic

Min

Max

Units

Conditions

100

THIGH

Clock high time

100 kHz mode

2(TOSC)(BRG + 1)

—

400 kHz mode

2(TOSC)(BRG + 1)

—

1 MHz mode(1)

2(TOSC)(BRG + 1)

—

101

TLOW

Clock low time

100 kHz mode

2(TOSC)(BRG + 1)

—

400 kHz mode

2(TOSC)(BRG + 1)

—

1 MHz mode(1)

2(TOSC)(BRG + 1)

—

102

SDA and SCL

rise time

100 kHz mode

—

1000

CB is specified to be from

10 to 400 pF

400 kHz mode

20 + 0.1 CB

300

1 MHz mode(1)

—

300

103

SDA and SCL

fall time

100 kHz mode

—

1000

VDD

≥ 4.2V

400 kHz mode

20 + 0.1 CB

300

VDD

≥ 4.2V

TSU:STA START condition

setup time

100 kHz mode

2(TOSC)(BRG + 1)

—

Only relevant for

Repeated START

condition

400 kHz mode

2(TOSC)(BRG + 1)

—

1 MHz mode(1)

2(TOSC)(BRG + 1)

—

THD:STA START condition

hold time

100 kHz mode

2(TOSC)(BRG + 1)

—

After this period, the first

clock pulse is generated

400 kHz mode

2(TOSC)(BRG + 1)

—

1 MHz mode(1)

2(TOSC)(BRG + 1)

—

106

THD:DAT Data input

hold time

100 kHz mode

—

400 kHz mode

0.9

107

TSU:DAT Data input

setup time

100 kHz mode

250

—

(Note 2)

400 kHz mode

100

—

TSU:STO STOP condition

setup time

100 kHz mode

2(TOSC)(BRG + 1)

—

400 kHz mode

2(TOSC)(BRG + 1)

—

1 MHz mode(1)

2(TOSC)(BRG + 1)

—

109

TAA

Output valid from

clock

100 kHz mode

—

3500

400 kHz mode

—

1000

1 MHz mode(1)

——

110

TBUF

Bus free time

100 kHz mode

4.7

—

Time the bus must be free

before a new transmission

can start

400 kHz mode

1.3

—

D102

Bus capacitive loading

—

400

Note 1: Maximum pin capacitance = 10 pF for all I2C pins.

2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but parameter #107

≥ 250 ns

must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL

signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the

SDA line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode) before the SCL line

is released.

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